Cyclone FPGA and DQ pins vs general purpose IO pins any HW difference?

Check the EMIF handbook:

https://www.altera.com/support/literature/lit-external-memory-interface.html

All devices have pins that are optimized for use as memory interfaces. You can see these highlighted in the Pin Planner by selecting an option from the View menu for external memory. Each set of DQ pins is associated with one or more DQS pins. The pin planner highlights these groups in different colors and amounts of DQ pins depending on the width you select (x4, x8/x9, etc.). You can use other pins with the soft IP, but they are not optimized for EMIF use. For hard IP (Cyclone V has it), you have to use specific pins.