Cyclone development board and its P30 Flash

Dear Sir/Madam

I am trying to program the Intel's Flash P30 using my FPGA. Could you please help me out, as i am having not luck. What i would like to do is store 16-bit binary word at certain locations. I am using VHDL, and my FPGA is using 1 Mhz, so that timming is not really a issue. So in the first clock cycle i assert the following signal as show below.

we<='0';

ce <= '0';

rs <= '1';

oe<='1';

adv <= '0';

and then in the next clock cycle

we<='1';

ce<='1';

A <=(others=>'1');--- address

DQ<="0000000000001010";--bit stream

This is what i understood from the datasheet, this should add my 16-bit stream in the location.

And to read what i have input i would assert the following signal

ce <= '0';

oe <= '0';

we<='1';

adv<='0';

Please do get back, as i am slighly stranded in my university project.

My vhdl code is below, and inorder to check that some data is stored i try to read the data and assign the last 4 bits to the LED on the board, but as the data is bi directional it seems to be show the correct LED lightling up, but if i was to removing the part of the code that writes data and only run the part which reads from that location now led's light up.

Please do get back, as i am slighly stranded in my university project and my Uni dont no much about such devices.

IBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY PT IS

PORT(

CLK_H : IN std_logic;

RS_H : IN std_logic;

A : OUT std_logic_vector (24 DOWNTO 0);

B : OUT std_logic_vector (3 DOWNTO 0);

adv : OUT std_logic;

ce : OUT std_logic;

clk : OUT std_logic;

oe : OUT std_logic;

rs : OUT std_logic;

we : OUT std_logic;

wt : OUT std_logic;

DQ : INOUT std_logic_vector (15 DOWNTO 0)

);

-- Declarations

END PT ;

-- hds interface_end

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ARCHITECTURE fsm OF PT IS

-- Architecture Declarations

TYPE STATE_TYPE IS (

s0,

s2,

s3,

s4,

s6,

s1

);

-- State vector declaration

ATTRIBUTE state_vector : string;

ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state" ;

-- Declare current and next state signals

SIGNAL current_state : STATE_TYPE ;

SIGNAL next_state : STATE_TYPE ;

BEGIN

----------------------------------------------------------------------------

clocked : PROCESS(

CLK_H,

RS_H

)

----------------------------------------------------------------------------

BEGIN

IF (RS_H = '1') THEN

current_state <= s0;

-- Reset Values

ELSIF (CLK_H'EVENT AND CLK_H = '1') THEN

current_state <= next_state;

-- Default Assignment To Internals

END IF;

END PROCESS clocked;

----------------------------------------------------------------------------

nextstate : PROCESS (

current_state

)

BEGIN

CASE current_state IS

WHEN s0 =>

next_state <= s2;

WHEN s2 =>

next_state <= s3;

WHEN s3 =>

next_state <= s1;

WHEN s4 =>

next_state <= s6;

WHEN s6 =>

next_state <= s6;

WHEN s1 =>

next_state <= s4;

WHEN OTHERS =>

next_state <= s0;

END CASE;

END PROCESS nextstate;

----------------------------------------------------------------------------

output : PROCESS (

DQ,

current_state

)

BEGIN

-- Default Assignment

-- Default Assignment To Internals

-- State Actions

CASE current_state IS

WHEN s0 =>

-- A <=(others=>'1');

--DQ<="0000000000000000";

WHEN s2 =>

we<='0';

ce <= '0';

rs <= '1';

oe<='1';

adv <= '0';

WHEN s3 =>

we<='1';

ce<='1';

A <=(others=>'1');

DQ<="0000000000001010";

WHEN s4 =>

ce <= '0';

oe <= '0';

we<='1';

adv<='0';

WHEN s6 =>

B <= DQ(3 downto 0);

WHEN OTHERS =>

NULL;

END CASE;

END PROCESS output;

-- Concurrent Statements

clk<=clk_H;

END fsm;

Thanking you in advance

Yours Sincerely

Dharmesh Joshi