Cyclone development board and its P30 Flash

Dear Sir

Thank you for your reply.

I have made changed to my VHDL code but found that it does not improve what i am trying to do. If possible could you further guide, please do note, that i havent erased the flash as my code for my other design is also on that design and iam using the last memory address to save my 16-bit word. I am also using the same clock that drives the state machine for the flash. Please do not that the all signals on the flash are asserted low. My VHDL code is below:LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY PT IS

PORT(

CLK_H : IN std_logic;

RS_H : IN std_logic;

A : OUT std_logic_vector (24 DOWNTO 0);

B : OUT std_logic_vector (3 DOWNTO 0);

adv : OUT std_logic;

ce : OUT std_logic;

clk : OUT std_logic;

oe : OUT std_logic;

rs : OUT std_logic;

we : OUT std_logic;

wt : OUT std_logic;

DQ : INOUT std_logic_vector (15 DOWNTO 0)

);

END PT ;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ARCHITECTURE fsm OF PT IS

-- Architecture Declarations

TYPE STATE_TYPE IS (

s0,

s3,

s4,

s6,

s1,

s5,

s7,

s2,

s8

);

ATTRIBUTE state_vector : string;

ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state" ;

SIGNAL current_state : STATE_TYPE ;

SIGNAL next_state : STATE_TYPE ;

BEGIN

clocked : PROCESS(

CLK_H,

RS_H

)

BEGIN

IF (RS_H = '0') THEN

current_state <= s0;

-- Reset Values

ELSIF (CLK_H'EVENT AND CLK_H = '1') THEN

current_state <= next_state;

END IF;

END PROCESS clocked;

nextstate : PROCESS (

current_state

)

BEGIN

CASE current_state IS

WHEN s0 =>

next_state <= s8;

WHEN s3 =>

next_state <= s1;

WHEN s4 =>

next_state <= s6;

WHEN s6 =>

next_state <= s6;

WHEN s1 =>

next_state <= s7;

WHEN s5 =>

next_state <= s3;

WHEN s7 =>

next_state <= s2;

WHEN s2 =>

next_state <= s4;

WHEN s8 =>

next_state <= s5;

WHEN OTHERS =>

next_state <= s0;

END CASE;

END PROCESS nextstate;

output : PROCESS (

DQ,

current_state

)

BEGIN

-- Default Assignment

-- Default Assignment To Internals

-- State Actions

CASE current_state IS

WHEN s0 =>

rs <= '0';

CE<='0';

WE<='0';

oe<='1';

adv <= '1';

B<=(others=>'1');

WHEN s3 =>

A <=(others=>'1');

DQ<="0000000000001010";

we<='0';

adv <= '0';

WHEN s4 =>

oe <= '0';

A <=(others=>'1');

adv <= '0';

WHEN s6 =>

B <= DQ(3 downto 0);

WHEN s1 =>

we<='1';

adv<='1';

WHEN s5 =>

we<='1';

WHEN s7 =>

DQ<="0000000000000000";

we<='0';

adv <= '0';

A <=(others=>'1');

WHEN s2 =>

we<='1';

adv<='1';

WHEN s8 =>

rs<='1';

WHEN OTHERS =>

NULL;

END CASE;

END PROCESS output;

-- Concurrent Statements

clk<=clk_H;

END fsm;

Please do advice me

Thank You

Regards

Dharmesh Joshi