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Honored Contributor
Honored ContributorCyclone 5 custom board PLL issues
I created a board for cyclone 5 soc 5CSEBA5U19. The design behaves in a strange way. (hardware design) The JTAG chain has the HPS then the FPGA in series, like in DE1-SOC eval board. The FP...
Altera_ForumHonored Contributor
Honored ContributorPin connection guidelines and Device Handbook say RREF_TL is related to Gigabit transceiver operation only, the pin is only available in GX and GT device variants. I don't see an indication that it affects general purpose PLLs.
