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Altera_Forum
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9 years ago

Cyclone 5 custom board PLL issues

I created a board for cyclone 5 soc 5CSEBA5U19. The design behaves in a strange way. (hardware design) The JTAG chain has the HPS then the FPGA in series, like in DE1-SOC eval board. The FP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I also thought that it should lose lock sometimes because of the supply. But believe me that is not the case.

I tried feeding the PLL with 50Mhz and 25Mhz and modified the PLL parameters to accept this but nothing worked. I also revised the PLL parameters many times. I checked the fitter report to see the min and max locking frequency and my input is in range.

I enabled the auto reset and disabled it but nothing worked. I

I also simulated the PLLs and the simulation was good.

I have some more boards that I can assemble and will check if this issue is repeated in the third board.

Thanks