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Honored Contributor
Honored ContributorCyclone 5 custom board PLL issues
I created a board for cyclone 5 soc 5CSEBA5U19. The design behaves in a strange way. (hardware design) The JTAG chain has the HPS then the FPGA in series, like in DE1-SOC eval board. The FP...
Altera_ForumHonored Contributor
Honored ContributorNo locking at all sounds dubious, I would expect temporary loose of lock with noisy supply.
Can it be that the PLL parameters are marginal for some reason? Can you feed the PLL with a variable clock generator to see if it locks at different frequency? Did you check the PLL parameters for plausibility? Did you see PLL output if you uncheck the automatic reset option?
