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Altera_Forum
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15 years ago

Cyclone 4 with DDR memory interface?

Hi. Having used FPGA's since the dark ages, I am making a decision to use either the Cyclone 4 or the Cyclone 3 with a NIOS II processor core. This is NOT a NIOS question. I have been reading...
Altera_Forum's avatar
Altera_Forum
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15 years ago

As kevin says there is no parallel OCT in Cyclone III either.

Depending on your set-up you can look into using series termination. E.g. If you only have one DDR2 device you can use OCT series termination not only for the address and command lines, but also for the DQ and DQS lines coupled with additional series termination resistors at the DDR2 device's side. This gives you the minimum amount of external terminating resistors. You have to disable ODT in the DDR2 controller. And you have to account for the extra rise time (== additional delay) in the timing constraints.