Cyclone 4 ALTPLL wrong freq output

Question

I used EP4CE55F23I7 in a custom board.

The problem is that the output of the ALTPLL is wrong. Input clk freq is 50Mhz. ALTPLL output clk freq is around 100KHz although I configured it to an output frequency in MHz (100MHz or other values). I knew the frequency by connecting one output pin of the FPGA to the oscilloscope. The lock pin of the PLL is zero.

We soldered two boards and the problem is the same.

The same board design was manufactured a while ago and was working. The new two boards were recently manufactured.

The FPGA can be programmed successfully using the SOF and the JIC files. The problem exists if I use the SOF or the JIC.

I checked the power regulators and they are working as expected.

Has anyone here faced a problem like this?

altera_forum · Answer

Hi,

1. Have you checked that pins VCCA, VCCD_PLL, and GNDA are properly connected to power supply?

2. Have you checked noise, riple ect. in those power rails?

3. Have you checked your reference clock with scope?

4. Do you use PLL with parameters generated with megawizard?

altera_forum · Answer

I checked the power supplies.

The reference clocks are ok. BTW this problem is for two input clocks at two different pins (Each one is LVDS at banks 2 and 5)

I generate the clocks using the ALTPLL using the IP Catalog quartus 15.1

Assume that noise exists, will this affect the FPGA and cause this strange behaviour?

In the previous board we did not have such a problem.

altera_forum · Answer

If some pin under the FPGA is not soldered correctly, will this cause the problem? like VCCA pin or VCCD? The package is BGA and I may not be able to check this.

altera_forum · Answer

There might be few main reasons for PLL to not work properly:

1. Excessive jitter on reference clock (check PLL input jitter specification in datasheet)

Personaly never had issues with jitter.

2. Power supply is not connected on VCCA VCCD_PLL GNDA pins.

I think that there ar very litle chance that you have two boards with same soldering issue. I would rather go for schematic error.

3. Power supply noise

Had this issue once. Check power suply noise requirements

4. Wrong PLL configuration.

altera_forum · Answer

The two boards behave strangely.

As I said before, two input clocks have this issue. But in one board, two output clocks from the two ALTPLL (driven by two independent clocks) are in KHz. In the second board, only one output is in KHz and the other output is not generated at all. So I think this may be related to pins soldering?

I still have few boards that are not soldered, only the FPGA is soldered and I may try to solder the other necessary components and try one last board before taking any decision.

The package is BGA so I cannot check if the pins are correctly soldered or not.

Thanks

Forum Discussion

Cyclone 4 ALTPLL wrong freq output

6 Replies

Recent Discussions

Error : Arria 10 emif_reset_ interrupt acknowledge

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

Agilex 7 HBM2E burst length

Agilex5 / IBIS HSIO - LPDDR4

[SOLVED] Cyclone V HPS I2C1 issue: no activity on bus