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Honored Contributor
Honored ContributorCyclone 4 ALTPLL wrong freq output
I used EP4CE55F23I7 in a custom board. The problem is that the output of the ALTPLL is wrong. Input clk freq is 50Mhz. ALTPLL output clk freq is around 100KHz although I configured it to an output...
Altera_ForumHonored Contributor
Honored ContributorI checked the power supplies.
The reference clocks are ok. BTW this problem is for two input clocks at two different pins (Each one is LVDS at banks 2 and 5) I generate the clocks using the ALTPLL using the IP Catalog quartus 15.1 Assume that noise exists, will this affect the FPGA and cause this strange behaviour? In the previous board we did not have such a problem.
