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Altera_Forum
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13 years ago

Cyclone 3 internal oscillator documentation

I used MegaWizard to instantiate the ALTINT_OSC internal oscillator of the Cyclone 3 FPGA. To learn about it I went to the Documentation button and downloaded what it brought up. But its a document called ug_lpm_alt_mfug which documents a lot of other functions but nothing about a clock.

Can't find any documents on this clock function at all. Its very simple with just an enable pin and a clock output pin. When I simulate it I get an 80 MHz clock. OK, so that's what it does.

I actually wanted something that represented the internal DCLK signal that clocks the external serial memory process during configuration. That is supposed to be a clock that is about 30 to 40 MHz and is automatic. If I wanted to use that as the clock to the ASMI component for writing to the serial memory, how would I get that clock signal? The ALTINT_OSC seems to be something different.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    ALTINT_OSC is a newly introduced Megafunction. Previously, no option to connect the internal oscillator to FPGA logic fabric had been provided by Quartus. Apparently Altera didn't yet finish the documentation linked in MegaWizard, so the link goes to a different document.

    There's also no clear specification about oscillator frequency range. It has been mentioned as "80 MHz internal chip oscillator" related to CRC generation. My guess is that there's actually only one oscillator, divided down for different purposes. If it has the same PVT variation as the DCLK configuration oscillator, we can assume a 40 to 80 MHz range, typically 60 MHz. A tighter frequency range would require some kind of individual calibration and non-volatile parameter storage.

    P.S.: Two supplements:

    - The internal oscillator has been previously available in wysiwyg.cycloneiii_components

    - I measure a frequency of 57.69 MHz, which supports my above frequency range assumption
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I tried connecting the output of the ALTINT_OSC to ALTPLL's clock input but I'm getting the error below:

    inclk[0] of pll must be driven by a noninverted input ....

    It appears to be not possible to use a PLL to generate another clock. Or am i doing something wrong?

    Is there a way to check if the ALTINT_OSC clock output is routed to the FPGAs clock network?