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I will have to put that together. I don't really have a board design yet. It is currently all under prototypes. I connected the circuit together using wire wrapping techniques and soldering to a prototype board.
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Ah, I see. Then the fact that your IC is getting hot may be due to an ESD problem you created while building the board. If this was a nice "clean" PCB and you had the same issue on multiple instances of the PCB, then the issue could be a design error. In the case of a problem with a single instance, its a bit more difficult to assign "blame". Can you switch out the FPGA for another?
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One thing I've forgotten to answer you from the previous reply is the version and configuration Quartus. I'm currently using Quartus II 32 Bit version 13.1.0 Build 162, the unused pins is set to "As Input Tri-Stated with weak pull-up".
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Ok, then there should not be any driver conflict.
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Let me know if that is sufficient as a schematic diagram ...
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It sounds like you've implemented everything correctly.
Have you looked at your power-on waveforms? Are the regulator ramps monotonic? Do each of the power rails come on in sequence correctly? Does the nSTATUS pin deassert high, and does the AS mode configuration start (DCLK toggles)?
Cheers,
Dave
Honored Contributor
