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ivar_svendsen's avatar
ivar_svendsen
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone 10LP Power requirements

Hello, I am planning to use Cyclone 10LP (F484 BGA) with a 3.3V Active Serial configuration scheme. All Active Serial configuration pins are part of Bank 1. I hope to be able to use banks 5, 6 and ...
Configuration
Power
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello Ivar,

​

Thank you for reaching out Intel FPGA Community.

​

The POR circuit of the Intel® Cyclone® 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and that contain configuration pins during power-on. They must have a monotonic rise to their steady state levels. The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range within 50 ms.

For the recommended operating range for each individual power supply, you can refer to Table 3 in the Intel® Cyclone® 10 LP Device Datasheet.


Regards,

Aqid