Forum Discussion
ADTL_belveera
New Contributor
4 years agoCyclone 10GX device DDR3L & Parallel Flash devices pinouts
We are using the Cyclone 10GX FPGA device 10CX105YF672I5G along with Micron make DDR3L device MT41K128M16JT-125 and Spansion make 16-bit NIOS compatible CFI Flash device S29GL256P10TFI010 in our de...
AdzimZM_Altera
Regular Contributor
4 years agoHello,
It's strictly specific when you're making pin assignment for the DDR.
You should choose which IO Bank that you want to use as the Address and Command pins and as the Data pins.
The Pinout file will provide the information for each pin of the device.
You will find which DQ group that you have to used for your Data pins.
I'm not sure on multiple pins assigned that you mentioned.
Can you provide the a snapshot of it?
You can confirm the pin connections that you have made by running the Fitter analysis.
From there you can see whether your configuration is right or wrong.
Regards,
Adzim