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GLees's avatar
GLees
Icon for Contributor rankContributor
2 years ago

Cyclone 10GX DDR3 EMIF Clock Input

I've instantiated a DDR3 EMIF in banks 2K & 2J (1.5V I/O) of a Cyclone 10GX220 device. I let Quartus choose the pin locations. Quartus assigns a differential clock with an LVDS interface for the pll_ref_clk input. I have two questions;

1. Can I force Quartus to accept a single ended, 1.5V clock instead?

2. If not, will the 1.5V I/O bank actually accept an LVDS clock? Typically a 1.8V I/O bank is used for LVDS signals.

1 Reply

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    "1. Can I force Quartus to accept a single ended, 1.5V clock instead?"

    • Yes the PLL reference clock can be single-ended clock or differential clock.


    "2. If not, will the 1.5V I/O bank actually accept an LVDS clock? Typically a 1.8V I/O bank is used for LVDS signals."

    • Yes there are dedicated clock pins in the I/O bank for the PLL reference clock.
    • Setting this clock pin to use LVDS I/O standard should be fine.


    Regards,

    Adzim