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Bohris's avatar
Bohris
Icon for New Contributor rankNew Contributor
5 years ago

Cyclone 10 use bank 2L for an LVDS clock input

Dear All, we are using Cyclone 10 (10CX105YF780E6G) with an external memory interface (DDR3 Scheme 2, 800MHz). DQS groups and RZQ are placed in I/O bank 2K, address/command in I/O bank 2L. The DQS...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello Bohris,

I am sorry to tell you that there is no condition that allows you to do that. Each I/Os in each banks work independently. The idea is that we want the fastest and shortest route for our IOs. Taking IOs from another bank will make it inconvenient and longer. I hope this answer helps.

Thanks