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3 Replies
- Altera_Forum
Honored Contributor
Hi,
Using QSYS/Platform designer design a system, With SIP IP and export the interface and connect physically to the FRDM-25KLZ board. Set appropriate slave/master configuration in SPI IP. https://www.alteraforum.com/forum/attachment.php?attachmentid=14665 Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
Honored Contributor
thank you so much
- Altera_Forum
Honored Contributor
where to give the inputs,as I m supposed to generate a clock of 1 MHZ.we is the testbench and how to generate it.