Forum Discussion

New Contributor

4 years ago

Cyclone 10 LP : fallback bitstream

Hello, I am new to the Cyclone 10 LP FPGA. I am looking for a way to handle a fallback bitstream in case the application bitstream update fails due to a power loss or something. I saw two docume...

Steve-534B46

New Contributor

4 years ago

Hi Bruce,

I was wondering if there is a document that attests to this information?
Indeed, the following document (https://www.intel.com/content/www/us/en/support/programmable/articles/000076544.html) does not mention the ASx4 mode for the Cyclone 10 LP family.

Thanks in advance for your help.

Best regards,

Steve

Forum Discussion

Cyclone 10 LP : fallback bitstream

Recent Discussions

DK-DEV-AGI027-RA QSPI Verification Fails

Cyclone 5 SoC FPGA Bank Supply Prerequisite

AGILEX 5 Migration issue

To INTEL - Request for Compliance Data from Analog Devices, Inc

Arria 10 GX RX max intra-differential pair skew