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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Cyclone 10 GX EMIF PLL clock input

After compiling a EMIF for Cyclone 10 GX, I noticed that it insists on using an external differential clock. Attempts at routing internal PLL output to pll_ref_clk input results in error. Does that...
FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hello,

is this also applicable for Arria 10devices?

I have found a source that states that in Quartus II 14.1 and earlier, this was also not possible for Arria 10 FPGA, but I have the same problem with Quartus 17.1.

Why is it not possible to generate the EMIF ref clk with a PLL? The *_readme.txt file says, that the ref clk is optional.

Best regards