Cyclone 10 GX EMIF PLL clock input

Hi,

--- Quote Start ---

After compiling a EMIF for Cyclone 10 GX, I noticed that it insists on using an external differential clock

--- Quote End ---

• This is user configurable option in C10 EMIF IP under PLL refclk section.

• Set in EMIF IP thenuse the IO standard that being set in EMIF IP.

--- Quote Start ---

Attempts at routing internal PLL output to pll_ref_clk input results in error

--- Quote End ---

• Yes, this is expected. C10 EMIF PLL refclk need to come externally from board.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)