Cyclone 10 GX DDR interface timing / constraint issue

I am still wondering where the half clock speed, synchronous clock for the interface is supposed to be coming from. I looked at the design and I understand generally how this is supposed to be hooked up but it requires that half speed clock that I don't know where to take from.

Again my interface has DDR data lines and a clock. The phylite calls the clock a strobe and then wants a clock that is synchronous to the strobe and half speed. But the ADC that I am interfacing with doesn't have that. Can it be generated by a PLL or something like that?

Thanks!