Honored Contributor
Honored Contributorhey dave, let me tell you what my partner and I did so far:
-we had the CDR set to LTD constant(is this bad?) -we tried a loopback, my partner told me the data came in correct just shifted(the PMA and PCS layers of the transceiver are okay, which was what I was worried about). -we changed the capacitor to a lower value ( was 0.1uf, changed to 2nf) -we tried numerous code methods (8b\10b, different word alignments, constant data, counters) none of these worked, the strange loss of data is still there, but since the loopback proved the altgx fabric is fine (unless I'm wrong and it's not a reference to prove that.), we can assume this is still a physical issue. something I'm worried about is the distance of the AC coupling capacitors from the FPGA, it's quite a long distance(see image) and I think this might be an issue for AC-coupled high data rates.
