Cyclon III - DDR2 signal integrity

I am having issues with my interface between a Cyclone III and external DDR2 SDRAM. The design works for a small period (between 15 and 30 mins) and then stops. I have traced this down to the external RAM and now I think its the signal integrity between the FPGA and external RAM.

I am using the Altera DDR2 SDRAM controller with ALTMEMPHY and I have run the TCL script to set my IO standards. This is SSTL-18 Class I. I have external 56R pull ups on all the appropriate lines and decoupling caps. The RAM is only 10mm away from the FPGA and I have used this hardware for previous projects without any issues.

However, now the peak voltage of my clock to the RAM is varying in amplitude between 1.3V and 2.4V instead of staying around 1.8V. This only occurs when the FPGA is accessing the RAM, otherwise its a nice clean clock. I fear that this is eventually going below the threshold level for the RAM, hence the failure of the design. The other signals such as the DQ bus is also varying slightly in amplitude but not to such a large degree.

I have tried reducing the drive strength, increasing the slew rate, including output termination series resistors, changing the IO standard, but nothing seems to make a difference to this problem.

My SDRAM interface is on banks 3 & 4 and is the only interface on those banks.

Does anyone have any ideas what would be causing this and how to improve things? Any help would be greatly appreciated as this problem has been going on for some time now. Thanks in advance.