--- Quote Start ---
HI,
thank you for reply,
the MSEL lines are wired to value of 2, means R42 mounted with value of "0" ohm, R39 mounted with value of "0" ohm, R30 mounted @0hm, R41, R29 and R40 are absent-.
thank you, please help with any other suggestions
thank you
maurizio stefani
--- Quote End ---
That should work. I would then check that the power supply power up meets the FPGA specs (ie, power supply sequencing, ramp rates are as required). I would also check for any unintended PCB solder shorts on the FPGA device. Do you have another board, and if so does it behave identically?
Your signal waveforms as shown in your first post show a substantial amount of noise. It could be real, or it could be due to how your probes are attached. It would be interesting to see the DCLK and DATA waveforms at a more expanded scale (ie, higher horizontal resolution).
Honored Contributor
