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Can anyone tell me what each of the three clock rates should be for
fast clock, slow clock, and read clock? It sounds like they should be:
fast clock = data rate / 2,
data rate = 7 * 65MHz
fast clock = 227.5MHz??
slow clock = 65MHz??
read clock = 2 * fast clock / DESERIALIZATION_FACTOR = 65MHz
read clock = 2 * 227.5 MHz / 7 = 65MHz??
Why the need for two 65MHz clocks here? Are they phase shifted from each other? By what amount?
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De-serialisation is done using DDR circuitry -> so the fast clock is 65 * 7 / 2 = 227.5 MHz. Because we can not directly do something with an odd factor, the ALT-LVDS block deserialises two subsequent transmissions and it needs a clock to synchronise the resulting 14 shifted bits using base clock divided by 2 -> 32.5 MHz. If you use the sync/multiplexer output options (not using M9K RAM blocks) the 14 bits are then fed into a multiplexer which uses this same 1/2 clock to select the first or second 7-bit output word. Finally you the use the third 1-to-1 pll clock output (-> 65 MHz) to drive the logic receiving the output of the multiplexer.
A good idea is to just compile the MegaWizard generated ALT_LVDS function on its own and then look in Tools->Netlist Viewers-> RTL Viewer what it produces.
If, for comparison, you generate the block with an internal PLL, as FvM suggests, you can see that the phase shift needed for the all three clocks is minus 1/2 of the bit-time (look in side any of the 3 generated .v files), and that the PLL has been set up in source-synchronous mode. Once again, in RTL Viewer you can appreciate how the generated clocks are used.
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Remember that if you generate one with an internal PLL, create an .sdc that has "derive_pll_clocks" in it. This should add multicycles from the fabric to the LVDS block that you can just copy into your design.
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How does the "derive_pll_clocks" add the multicycles? What if we use an external PLL?
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