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Altera_Forum's avatar
Altera_Forum
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15 years ago

cyc3 LVDS_RX for camera link

I want to instantiate an ALTLVDS_RX megafunction and an external PLL in my design for the purpose of deserializing camera link video. The camera I am using runs at 65MHz for a pixel clock. ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I can't answer the question in detail, but if you want to know which PLL settings are expected by the LVDS_RX block, you can implement a variant with internal PLL and see, how the PLL is set up.

An odd deserialization factor is involving a rather complex structure, because fast clock uisn't an integer multiply of slow clock.