Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCustom PCB Design
Hi, I'm done with verification of my design on Altera's S3 dev board and doing the schematic of my own board. My plan is to derive my board from the dev board. Is this a good way of practice? ...
Altera_ForumHonored Contributor
Honored ContributorPossible speed enhancement of an USB Blaster clone is of course limited by the USB FS throughput below 12 MBit/s. Furthermore, some Altera devices have a TCK limitation of 10 MHz (e.g. MAX7000S, MAX9000, ACEX1K). So a faster clock than 6 MHz isn't an option for a universal JTAG programmer, but possible for a dedicated FPGA interface.
Cyclone III could use up to 25 MHz, in principle. JTAG data lines are by design set on TCK falling edge and sampled on rising edge. Cyclone III already consumes up to 15 ns of the 20 ns delay margin on output, so JTAG communication would fail with only 5 ns additional delay. In practice, 24 or 25 MHz would require to change the data sampling phase in the CPLD, too. Finally, I doubt, if the software driver stack allows for a considerably higher throughput than 6 MBit/s.
