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Altera_Forum's avatar
Altera_Forum
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16 years ago

Custom PCB Design

Hi, I'm done with verification of my design on Altera's S3 dev board and doing the schematic of my own board. My plan is to derive my board from the dev board. Is this a good way of practice? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

There was at least a downloadable verilog module somewhere on the World Wide Waiting a couple of years ago. 

module jtaghelp(clkin, resetn, usbtxen, usbrxfn, usrtdo, nstatus, clkout, usbrdn, usbwr, usrtck, usrtms, nce, ncs, usrtdi, led, tspin, usbd);

Haven't checked it yet, it looks very promising to be right one

But it would be worth to give it a try mostly if there is chance in speeding up the jtag a bit what would increase the overall speed of GDB useage as well as SignalTap.

From the source the "real" TCK is Bit 0 of the raw bit banged data. but the statemachine around it needs at least 3 clock cycles (IDLE GETCMD USECMD) in a loop so the TCK will be 24MHz / 3 = 6MHz

The question is, what are the limits ?

JTAG speed of the target devices and the pcb ? as well as the FTDI interface ...