New Contributor
Regular ContributorHi Oleg,
Is there any time gap between the clock reception and the valid data reception? PLL will take this delta time to get locked and be ready to capture the data when it arrives. Is it configurable in the sensor?
For Cyclone 10 LP, the PLL can take max 1ms to lock to the input.
Seems like you have a mechanism to detect the presence of input clock based on which you are trying to control the pfdena signal.
If that is possible, then you can use that mechanism to control the clkswitch input to switch between two different clock inputs.
Please note that the PLL's two clock inputs need not necessarily be at the same frequency. They can be different as well. Refer: https://www.intel.com/content/www/us/en/programmable/documentation/sxm1481253171919.html#xbq1490068123558
Regards.
New ContributorYes, at current settings the time between valid clock and vallid data is about 2 us. The pll is able to lock quick enough if I use pdfena.
When using switchover with two different signals, the lock time is much higher, than between similar frequencies. Thats why I wrote about method's disadvantage.
