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AlehTS
New Contributor
New ContributorCSI-2 receiver
Hello.
I am designing CSI-2 receiver on Cyclone 10LP device. The data are comming from sensor.
CSI clock is about 350 Mhz, 4 data lanes.
At the data inputs I use altlvds_rx. Due to high data ra...
AlehTSNew Contributor
New ContributorI've made some experiments with pdfena and switchover.
1. Switchover. When I switch from one 100 MHz source to another 100 MHz source, the pll locks in ~300ns. Not bad. The disadvantage - I have to know the exact CSI clock and produce the same by additional pll.
2. pfdena. When pdfena is inactive, the PLL frequency slowly changes. The longer inactivity time, the bigger the difference. With inactivity time is 200 us and 100 MHz at the input, the lock time is also ~300ns. The higher input frequency, the shorter lock time.
At this point looks like pll will be locked quick enough. The tests will show.
