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AlehTS
New Contributor
New ContributorCSI-2 receiver
Hello.
I am designing CSI-2 receiver on Cyclone 10LP device. The data are comming from sensor.
CSI clock is about 350 Mhz, 4 data lanes.
At the data inputs I use altlvds_rx. Due to high data ra...
AlehTSNew Contributor
New ContributorUsing LP signals I can determine the mode change events.
I am thinking about using "pfdena" signal to disable input detection during low power mode.
The second thing I am thinking about is using "Switchover". I'll use interanlly generated clock with allmost the same frequency as a "backup" clock.
But I am not sure how fast the pll can switch between close frequencies or lock after pfd is enabled.
