Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Critical Path Delay Calculation: Component Delay information

Hi, I am trying to calculate the clocking scheme for a datapath unit (DU). Say I want to improve the clocking speed by applying multi stage pipeline to the DU, I need to know the delay of the l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Did you try giving constraints in SDC and compiling the design?