Creating pipeline registers

Hi,

I'm trying to create a pipeline register for the IFETCH stage on a simple processor and I've hit a roadblock. The specific question I have is on how to pipeline the 32-bit instruction.

I have pipelined the PC+4 signal, but I don't know how to do it with the Instruction coming out of the "Instruction memory". In "PORT MAP", q_a => Instruction, but I don't know what q_a is.

The PC is 10 bits and goes into the "Instruction Memory" stage and obtains a 32 bit instruction: 5 is for $1, 5 for $2, 5 for opcode?, some(?) goes to control bit and some goes to the sign extend.

The question is, how do I get the that 32 bit Instruction so I can store it in a register to pipeline it. I've attached the code in the bottom.

I tried to create a new register D_Instruction (31 DOWNTO 0) and then set it to the Instruction at the clock cycle then, set the q_a to D_Instruction.

Thanks for your help!

-- Ifetch module (provides the PC and instruction

--memory for the MIPS computer)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.all;

ENTITY Ifetch IS

PORT( SIGNAL Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );

SIGNAL PC_plus_4_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );

SIGNAL Add_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );

SIGNAL Branch : IN STD_LOGIC;

SIGNAL Zero : IN STD_LOGIC;

SIGNAL PC_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );

SIGNAL clock, reset : IN STD_LOGIC);

END Ifetch;

ARCHITECTURE behavior OF Ifetch IS

SIGNAL PC, PC_plus_4 : STD_LOGIC_VECTOR( 9 DOWNTO 0 );

SIGNAL next_PC, Mem_Addr : STD_LOGIC_VECTOR( 7 DOWNTO 0 );

-- Pipeline register

SIGNAL D_PC_plus_4 : STD_LOGIC_VECTOR( 9 DOWNTO 0 );

SIGNAL D_Instruction : STD_LOGIC_VECTOR( 31 DOWNTO 0 );

BEGIN

--ROM for Instruction Memory

inst_memory: altsyncram

GENERIC MAP (

operation_mode => "ROM",

width_a => 32,

widthad_a => 8,

lpm_type => "altsyncram",

outdata_reg_a => "UNREGISTERED",

init_file => "program.mif",

intended_device_family => "Cyclone"

)

PORT MAP (

clock0 => clock,

address_a => Mem_Addr,

q_a => D_Instruction );

-- Instructions always start on word address - not byte

PC(1 DOWNTO 0) <= "00";

-- copy output signals - allows read inside module

PC_out <= PC;

PC_plus_4_out <= D_PC_plus_4;

-- Pipeline register

D_PC_plus_4 <= PC_plus_4;

-- send address to inst. memory address register

Mem_Addr <= Next_PC;

-- Adder to increment PC by 4

PC_plus_4( 9 DOWNTO 2 ) <= PC( 9 DOWNTO 2 ) + 1;

PC_plus_4( 1 DOWNTO 0 ) <= "00";

-- Mux to select Branch Address or PC + 4

Next_PC <= X"00" WHEN Reset = '1' ELSE

Add_result WHEN ( ( Branch = '1' ) AND ( Zero = '1' ) )

ELSE PC_plus_4( 9 DOWNTO 2 );

PROCESS

BEGIN

WAIT UNTIL ( clock'EVENT ) AND ( clock = '1' );

IF reset = '1' THEN

PC( 9 DOWNTO 2) <= "00000000" ;

ELSE

PC( 9 DOWNTO 2 ) <= next_PC;

END IF;

END PROCESS;

-- Processes for pipeline register : PC+4

PROCESS

BEGIN

WAIT UNTIL ( clock'EVENT ) AND ( clock = '1' );

IF reset = '1' THEN

D_PC_plus_4( 9 DOWNTO 0) <= "0000000000";

ELSE

D_PC_plus_4( 9 DOWNTO 0) <= PC_plus_4;

END IF;

END PROCESS;

-- Processes for pipeline register : Instruction

--PROCESS

--BEGIN

--WAIT UNTIL ( clock'EVENT ) AND ( clock = '1' );

--IF reset = '1' THEN

-- D_Instruction( 31 DOWNTO 0) <= "00000000000000000000000000000000000";

--ELSE

-- D_Instruction( 31 DOWNTO 0) <= Insruction;

--END IF;

--END PROCESS;

END behavior;