Create delay between internal logics

normaly you should have a fully syncronize design where all logic registers are based upon a clock and the combinatorical delay betwee nregisters does not matters, the synthesis and timing analyzer will show how high the clock rate could be

designing a delay in a full synchron design is normaly done with pipelining a register, but you will delay N clocks the signal.

asyncron delay is due to different combinatorical legth between register output and input. but trusting in such delays can be very risky as the delay time depends upon the device and temperature and other criteria so can't say how the delay will be. for example if the device is cooled down, it gets faster so the setup time is getting critical.

specifying a delay for example in verilog with a# is for simulation purpose only and has no effect to the real design in the target

Hi MSchmitt,

Okay, I actually don't quite get what you are saying. So, if for example, I wanted a particular combinational path to be 4ns, how can I do it? Thru timequest or ... any suggestion?

Pretty confused state,

Dave

ahh okay you want to specify that the output of register 1 to the input of register 2, whatever is in it, does not take longer than 4ns

yes that is timequest you will need to constrain that i haven't done such a sdc constrain yet

for this there are better sdc experts here, sorry

Hi MSchmitt,

Thanks for the reply. You got me right, and it can be either registers or simply any combinational logics. I get the idea that it is not easily implemented based on your reply, however I just wonder if there's any possibility. I hope the rest of the timing experts can comment further.

A little clear but still confused,

Dave

If you want a maximum delay from register to register of 4ns this is simply done setting the clock frequency, in the TimeQuest Wizard, to 250MHz.

Is this what you want to do?