create_clock with pre map signals....

Either nobody else has a clue, or this is such a clueless question no one wants to waste their time with it :)

For what it is worth, it does appear the (* keep = 1 *) and /* synthesis keep = 1 */ don't work with vqm files in particular. I guess I'm leaning towards one of two things

1) declaring that this feature only works in source code (modulo restrictions listed on page 9-47 of the user manual) before processed by the gui in particular ??

2) doing timing driven synthesis from the start may allow certain timing requirements to car through mapping to the fit stage... Otherwise, one needs to presume a clock net or device is there and won't be optimized away or else one always does timing interactively, which I have a hard time believing is the case (hmm, that certainly that's what timequest, etc, implies)...

I'll ping support and let y'all know what I find out...