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Honored ContributorCRC Calculation - VHDL
Hello to all forum members!!!
I'll be glad to get your's suggestions to solve my problem. I am interested to make the CRC Calculation as fast as possible (without using the MegaWizard function). In order to make the calculation as fast as possible, I used the "variables" and not the signals. The purpose of VHDL Code is doing something like 250 xor actions(5 actions on every byte while the data telegram build from 53 bytes). During the sumalition (ModelSim) I got the right results. Pending one clock the result is ready! Of course, it's uncompareable to real FPGA chip perfomance. I did the Quartus TimeQuest analyze with 50MHz oscillator. The result was really bad. The parameters that failed are:- Report SetUp Summary
- Fmax is something like 20Mhz
17 Replies
Altera_ForumHow many bits do you process in one clock cycle?
I have implemented the CRC32 with 64 bits in one clock cycle and can run it with 156.25 MHz in a Startix V without any problems. And this is a straight forward implementation without any pipelining. By the way it is possible to pipeline CRC computations. There is a bunch of publications that describe how to do this. The one that I currently favor is: y. sun, m.s. kim, "a table-based algorithm for pipelined crc calculation," 2010 ieee international conference on communication (http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5501903&url=http%3a%2f%2fieeexplore.ieee.org%2fxpls%2fabs_all.jsp%3farnumber%3d5501903)- Altera_Forum
And ....
You can do a CRC16 with 5 XOR per byte (and some shifts which are free in harware), I doubt the same is true of CRC32. - Altera_Forum
It's CRC32 for MPEG-TS streams.
- Altera_Forum
Which CRC are you computing?
Sounds a bit like CRC16. You might be able to make use of the fact that you can XOR together two packets and still have a valid CRC (if you correctly allow for the initial value and final inversion). So maybe you can xor together the CRC value for each bit. While this is now 53*8 XORs, they can be done in parallel - so only 10 deep. If large parts of the packet are fixed, they can be excluded from the dynamic crc. OTOH why don't you defer the CRC calculation until teh data is serialised? - Altera_Forum
Why? Use signals and parallelize all the stuff as much, as possible. We use CRC32 with signals giving result in 1 clk cycle.
- Altera_Forum
But if I choose to use "signals" it can take something like 250 cycles at least. Also, I have to say that every next value is dependent from the previous one.
What do you mean when you are talking "think about the circuit" ? To build circuit by myself from logic elements? Do you have the good explanation for the pipeline maybe? I tried to seek the good topic about it but didn't find anything seriously...Maybe do you have the good code example to pipeline? Tnx for your answer - Altera_Forum
to increase the fmax, you need to pipeline the design. 250 XORs is a lot to do in a single clock. And to do that you'll need signals not variables. Before you design ANYTHING with VHDL, you need to think about the circuit before you write any code.
