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Altera_Forum's avatar
Altera_Forum
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13 years ago

CRC Calculation - VHDL

Hello to all forum members!!! I'll be glad to get your's suggestions to solve my problem. I am interested to make the CRC Calculation as fast as possible (without using the MegaWizard function)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

to increase the fmax, you need to pipeline the design. 250 XORs is a lot to do in a single clock. And to do that you'll need signals not variables. Before you design ANYTHING with VHDL, you need to think about the circuit before you write any code.