CRC Calculation - VHDL

Which CRC are you computing?

Sounds a bit like CRC16.

You might be able to make use of the fact that you can XOR together two packets and still have a valid CRC (if you correctly allow for the initial value and final inversion).

So maybe you can xor together the CRC value for each bit.

While this is now 53*8 XORs, they can be done in parallel - so only 10 deep.

If large parts of the packet are fixed, they can be excluded from the dynamic crc.

OTOH why don't you defer the CRC calculation until teh data is serialised?