CRC Calculation - VHDL

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How many bits do you process in one clock cycle?

I have implemented the CRC32 with 64 bits in one clock cycle and can run it with 156.25 MHz in a Startix V without any problems. And this is a straight forward implementation without any pipelining.

By the way it is possible to pipeline CRC computations. There is a bunch of publications that describe how to do this. The one that I currently favor is:

y. sun, m.s. kim, "a table-based algorithm for pipelined crc calculation," 2010 ieee international conference on communication (http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5501903&url=http%3a%2f%2fieeexplore.ieee.org%2fxpls%2fabs_all.jsp%3farnumber%3d5501903)

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I am trying to do CRC on full packet (8 bit * 53 = 424)

I'm still not understanding, how does it possible to make the multiply CRC calculation during 1 cycle and with "signals" when your are dependent of the previous value. Every time I have to wait to the end of the cycle in order to get the result