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Altera_Forum
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14 years ago

CPLD VHDL problem

HI, I am trying to understand the operation of the following VHDL code. The cpld EPM2210 is attached to a processor bus (d0-d15 and A0-A15). When I do a double read 'word aligned' address rang...
Altera_Forum's avatar
Altera_Forum
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14 years ago

It's not clear to me, what the code is expected to do. As coded, the state machine advances on every clock cycle while read is active. The result depends on the relation of clock and processor bus timing.