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Honored Contributor
Honored ContributorCPLD VHDL problem
HI, I am trying to understand the operation of the following VHDL code. The cpld EPM2210 is attached to a processor bus (d0-d15 and A0-A15). When I do a double read 'word aligned' address rang...
Altera_ForumHonored Contributor
Honored ContributorI would primarly ask what kind of process and trigger condition is including the FIFO counter and assignments of state_rd_fifo. A counter or a state variable register can only work under a clock edge sensitive condition, e.g if rising_edge(clk).
