CPLD VHDL problem

Thanks FvM,

Your right I need to open my eyes and wakeup!!

I changed the code so that at the same address (0xxxxxx42) I could read in 24 alternative words. i.e. in this case 24 off (0x1234 and 0x789a).

Can anyone think of why this code does not do this simple task.

when "0000000001000010" => -- read 24 double words

case state_rd_fifo is

when idle_state =>

fifo_enable_read <= '1';

proc_data (15 downto 0) <= X"1234";

fifo_enable_write <= '0';

state_rd_fifo <= read_top_16;

when read_top_16 =>

end_fifo_24_words:= end_fifo_24_words+1;

state_rd_fifo <= idle_state;

proc_data (15 downto 0) <= "789a;

fifo_enable_read <= '0';

if end_fifo_24_words >= 24 then

state_rd_fifo <= idle_state;

end_fifo_24_words:= 0;

end if;

when others =>

state_rd_fifo <= idle_state;

end_fifo_24_words:= 0;

proc_data (15 downto 0) <=

"ZZZZZZZZZZZZZZZZ";

end case;

when others => proc_data (15 downto 0) <=

"ZZZZZZZZZZZZZZZZ";

end case;