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Altera_Forum's avatar
Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

It's a caveat with naming and name matching in the SDC.

When you put the B assignment into the clocked process, you get a registers named B[...]~reg instead of rb[...].

These match the B* patterns in the multi-cycle exceptions, which causes havoc. The transfers from ra[...] to B[...]~reg are now subject to the same 2/0 multi-cycle and they can't meet the hold requirement.

If I had properly selected the paths, with [get_ports B[*]], you wouldn't have had such problem.