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Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Taking josyb's project, I made it meet timing with the MAX V by

a) using the rising edge to capture A.

b) applying a multi-cycle exception of 2/0 to paths from A.

c) applying a multi-cycle expcetion of 2/0 to paths to B.