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Honored Contributor
Honored ContributorCPLD selection suggestion
Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_ForumHonored Contributor
Honored ContributorPranchi,
do not pay too much attention to the datasheet values, as this can be design dependent. You need to make a test design, apply timing constraints and see if it can meet them, as josyb did. Would the I/O timing improve if you use the reverse edges? Ie, use the rising edge to capture the data and use the falling edge to transmit data? (I don't have access to Quartus right now)
