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Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The input and output timings are very close throughout a CPLD (or FPGA) family.

There is no 'real' 297 MHz clock involved, but in transferring the data from the negative edge, used by input A, to the positive edge, used by output B, you only have half the period of the 148.5 MHz clock , which is 'equivalent' to a 297 MHz clock.