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Altera_Forum's avatar
Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Did anyone try to make a Max V project to document what he/she is saying?

I did. And a Max V can handle the transfer of the negative clock to the positive clock edges for the internal registers. But it fails at both the input and output setup times as Max V doesn't have either input nor output registers. I had to switch to a Cyclone IV speed grade 6 to meet the interface timings.