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Honored Contributor
Honored ContributorCPLD selection suggestion
Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_ForumHonored Contributor
Honored ContributorYes, the problem is really there. Yes, you can clock the signal in OK and through a couple of FFs if you feel the need. However, at some point, if you need to clock it out on the other edge, you only have half a clock cycle to transfer the data between FFs. You would need to meet the setup time required of the 297MHz clock frequency that Tricky referred to.
