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Altera_Forum's avatar
Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hmm?

I really can't see the problem here.

All he needs is to implement a chain of registers inside the CPLD. The first level of registers has to work on the falling edge, the last one on the rising edge.

He'll need 3 or maybe 4 levels of registers to meet the timing between the oposite edges, but a MAX II/V should be able to do it.

Just try it in Quartus and see if can meet the timing constraint.