CPLD selection suggestion

As Tricky and Alex pointed out, I believe the CPLD solution would transfer the timing problem inside the CPLD, with more delays to take into account.

If it's simply a problem of synchronizing / changing the clock edge between device A and B, maybe including a single logic port (buffer or inverter) on the clock line driving one of the devices could make everything working. I don't know your actual design, so maybe this is not feasible in your case, because it arises other timing problems.