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Altera_Forum
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12 years ago

CPLD selection suggestion

Hi, We want to interface two devices (A and B) working at 148.5MHz. The first device (A) gives out data at the negative edge and the second device (B) captures at the positive edge. The cl...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi Tricky,

Thank you for your quick reply.

If we use a CPLD with an internal PLL, then can it capture at falling edge and give out at rising edge? In this case we can add phase shift to the clock signal.

Regards,

Prachi